DCVS (Differential Cascode Voltage Switch) circuits, developed for VLSI applications, are capable of providing high functional density and performance. Such circuits comprise "tree" clusters of active device pairs which operate as discrete logic circuits. Each tree receives complementary input signals on pairs of conductors, and produces an output signal having a predetermined logical relation to the input signals. The output signal, presented on a pair of conductors, is in a "legal" state only if the signals on the respective conductors are at different levels, and in an "illegal" state otherwise.
Presently, the paired conductors on which input and output signals are conveyed relative to trees are termed "2-track" or "dual-track" connections". Dual-track connections consume more chip space and are more difficult to route through a chip than single-track (single wire) connections. However, single-track connections have not been considered feasible because they permit propagation of faulty signals between trees with essentially indeterminate effects.
It is also desirable to be able to test integrated logic circuits on a chip, including DCVS tree circuits. A simple presently well known testing technique involves arranging circuits to be tested in "level sensitive scan design" (LSSD) groups, and providing "scannable shift register latch" (SRL) circuits integral with each group. Test signals scanned into the SRL latches are applied to respective groups, the groups are operated for a clock cycle during which signals representing states of groups are scanned into SRL circuits (usually of other groups), and the signals then stored in the SRL circuits are scanned out for evaluation (fault detection and location) either off chip or on chip. The LSSD grouping is supposed to ensure that any fault conditions in a group can be detected and traced by one or more scan in/scan out operations.
Arrangements of this kind and their rationale are presented in "A Logic Design Structure For LSI Testability", E. B. Eichelberger et al, Proceedings of the 14th Design Automation Conference (1977), IEEE, pages 206-215 (hereafter referred to as the "Eichelberger paper").
It has been proposed also to use scannable shift register latches to facilitate testing of DCVS circuits. Refer, for instance, to U.S. Pat. Nos. 4,698,830 and 4,656,417, and IBM Technical Disclosure Bulletin, Vol. 27, No. 10B, pages 6148-6152, J. B. Hickson et al, "Testing Scheme For Differential Cascode Voltage Switch Circuits. However, these proposals have a number of shortcomings in that their implementations would require departure from existing (and proven) LSSD design practices, and not alleviate the previously stated use of 2-track connections between DCVS circuit groups.
Accordingly, the aim of this invention is to provide an arrangement of DCVS circuits which allows for routing of signals between DCVS circuits over single-track connections (hereafter also termed single-track global interconnect wiring), while permitting complete and accurate testing such that all faults including illegal output states of DCVS tree circuits are detectable and traceable.